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Simple DMA Transfer
Initially, a PCI Master writes to the four DMA control registers (cycles C0 to C7 in Figure 6-33 ). Three clock cycles
after the control register (CR) is written, the core asserts its PCI request signal REQN. When the PCI arbiter grants the
bus and the bus is idle, several clock cycles later the core initiates a PCI cycle asserting the MAST_ACTIVE output.
See cycle A2 in Figure 6-33 .
cycle
C0 C1 C2 C3 C4 C5 C6 C7
A0 A1 A2 A3 0
1
2
3
4
5
6
7
8
clk
framen
cben[3:0]
B
0
7
0
ad[31:0]
ADDR
PA
RA TC CR
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
reqn
gntn
dma_bar[2:0]
mast_active
dp_start
dp_done
bar_select[2:0]
wr_cyc
rd_cyc
rd_stb_out
rd_stb_in
0
mem_add[11:0]
000
004 008 00C 010 014
mem_data_in[31:0]
0
1
2
3
4
5
Figure 6-33 · DMA Burst Read Cycle Including DMA Start Sequence
Initially, the core turns on its AD and CBE outputs at the same time that it initiates a backend cycle. The backend
transfer is very similar to a Target transfer, except that the MAST_ACTIVE output is valid during the transfer. The
BAR_SELECT output will be set to the value set in the DMA control register.
82
v4.0
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